Vector generate mask instruction
AssigneeInternational Business Machines Corporation
InventorsJonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel
Life of this patent
Estimating the term…
Abstract
A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.
Claims20
A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising:
- a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation;
- a first register field to be used to designate a first register, the first register comprising a first operand;
- a first field to specify a starting position;
- and
- a second field to specify an ending position;
- and
- executing the machine instruction, the executing comprising:
- generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position.
A computer system for executing a machine instruction in a central processing unit, the computer system comprising:
- a memory;
- and
- a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
- obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation;
- a first register field to be used to designate a first register, the first register comprising a first operand;
- a first field to specify a starting position;
- and
- a second field to specify an ending position;
- and
- executing the machine instruction, the executing comprising:
- generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position.
A method of executing a machine instruction in a central processing unit, the method comprising:
- obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation;
- a first register field to be used to designate a first register, the first register comprising a first operand;
- a first field to specify a starting position;
- and
- a second field to specify an ending position;
- and
- executing the machine instruction, the executing comprising:
- generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position.
Dependencies are inferred from the claim text.