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US 2014/0208035 A1Published application
Cache circuit having a tag array with smaller latency than a data array
AssigneeIntel Corporation
InventorLarisa Novakovsky
Life of this patent
Estimating the term…
Abstract
A method is described that includes alternating cache requests sent to a tag array between data requests and dataless requests.
Claims19
A semiconductor chip, comprising:
- a cache comprising a tag array and a data array, said tag array having lower latency than said data array;
- a first cache request path that flows into said tag array;
- a second cache request path that flows into said tag array;
- logic circuity to determine whether a cache request is a data request or a dataless request, and, place said cache request onto said first cache request path if said cache request is a data request, or, place said cache request onto said second cache request path if said cache request is a dataless request.
1 more element
A method, comprising:
- alternating cache requests sent to a tag array between data requests and dataless requests.
A computing system, comprising two connected semiconductor chips, each of the two connected semiconductor chips, comprising:
- multiple processing cores;
- a cache with cache access circuitry, comprising:
- a cache comprising a tag array and a data array, said tag array having lower latency than said data array;
- a first cache request path that flows into said tag array;
- a second cache request path that flows into said tag array;
- logic circuity to determine whether a cache request is a data request or a dataless request, and, place said cache request onto said first cache request path if said cache request is a data request, or, place said cache request onto said second cache request path if said cache request is a dataless request.
3 more elements
Dependencies are inferred from the claim text.