Apparatus and method for memory-hierarchy aware producer-consumer instructions

An instruction processing apparatus comprising:

• a producer core within a central processor unit (CPU) producing data for one or more consumer cores and a cache accessible by the producer core and the one or more consumer cores;
• core-core producer-consumer logic configured to perform the operations of:
• writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
• upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
• setting an indication to indicate to the consumer core that data is available in the cache;
• and
• upon the consumer core detecting the indication, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

A computer system comprising:

• a graphics processor unit (GPU) for processing a set of graphics instructions to render video;
• and
• a central processing unit comprising:
• a producer core within a central processor unit (CPU) producing data for one or more consumer cores and a cache accessible by the producer core and the one or more consumer cores;
• core-core producer-consumer logic configured to perform the operations of:
• writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
• upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
• setting an indication to indicate to the consumer core that data is available in the cache;
• and
• upon the consumer core detecting the indication, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

An apparatus for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising:

• means for writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
• means for responsively generating an eviction cycle upon detecting that the designated amount of data has been written, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
• means for setting an indication to indicate to the consumer core that data is available in the cache;
• and
• means for providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.