Processor with tightly coupled smart memory unit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShyh-An CHI
Life of this patent
Estimating the term…
Abstract
An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.
Claims20
An information processor comprising:
- a central processing unit core;
- a direct memory access unit connected to the central processing unit core;
- and
- at least one tightly coupled smart memory unit connected to the central processing unit core, the at least one tightly coupled smart memory unit comprising:
- a memory unit;
- a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.
An information processor comprising:
- a central processing unit core;
- and
- at least one tightly coupled smart memory unit connected to the central processing unit core, the at least one tightly coupled smart memory unit comprising:
- a plurality of memory units;
- a plurality of local processing units;
- a plurality of registers adapted to be accessed by the central processing unit core and the plurality of local processing units,
- wherein each local processing unit of the plurality of local processing units is adapted to process data stored in a corresponding memory unit of the plurality of memory units or a corresponding register of the plurality of registers,
- wherein each memory unit of the plurality of memory units is adapted to be accessed by the central processing unit core and a corresponding local processing unit of the plurality of local processing units,
- wherein each local processing unit of the plurality of local processing units is configured to receive instructions from the central processing unit core or a register of the plurality of registers.
An information processor comprising:
- a central processing unit core;
- a direct memory access unit connected to the central processing unit core;
- and
- at least one tightly coupled smart memory unit connected to the central processing unit core and to the direct memory access unit by a bi-directional bus, the at least one tightly coupled smart memory unit comprising:
- a dual port memory unit;
- a local processing unit adapted to process data stored in the dual port memory unit, wherein the dual port memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.
Dependencies are inferred from the claim text.