Time-division multiplexed data bus interface
AssigneeApple Inc.
InventorsGirault W. Jones, Nathan A. Johanningsmeier, Casey L. Hardy
Life of this patent
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Abstract
An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0,1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed.
Claims22
A method for performing a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two, the method comprising
- the following operations performed over a plurality of frame intervals, by a first bus device and a second bus device that are coupled to a bus data line:
- driving a frame marker on the bus data line by the first bus device in slot 0, wherein the frame marker has a plurality of framer marker bits each being driven by the first bus device in a respective instance of slot 0 in the frame intervals;
- driving the bus data line with first device data in slot 1, by the first bus device;
- and
- driving the bus data line with second device data in an assigned slot other than slots 0 and 1, by the second bus device.
A time-division multiplexed data bus device comprising:
- a first modulator to receive a first data signal;
- and
- a first bus interface circuit having
- a multiplexor with a control input that is to receive a select signal synchronized with a clock signal,
- a frame marker generation circuit coupled to an input of the first multiplexor and responsive to the clock signal, wherein another input of multiplexor is coupled to an output of the first modulator,
- a switch circuit with a) an input coupled to an output of the first multiplexor and b) an output to be coupled to a bus data line, and
- a switch controller coupled to control the switch circuit responsive to the clock signal so that the switch circuit is enabled during slots 0 and 1 of a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two.
A time-division multiplexed data bus device, comprising:
- a bus interface circuit having
- a multiplexor with a control input that is to receive a select signal synchronized with a clock signal, a frame marker generation circuit coupled to an input of the first multiplexor and responsive to the clock signal, wherein another input of multiplexor is coupled to receive a data signal, a switch circuit with a) an input coupled to an output of the first multiplexor and b) an output to be coupled to a bus data line, and a switch controller coupled to control the switch circuit responsive to the clock signal so that the switch circuit is enabled during slots 0 and 1 of a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two;
- and
- a demultiplexor having an input coupled to the bus data line and a plurality of outputs each to produce a bitstream for a respective channel, controller logic to receive the clock signal and a frame marker produced by the frame marker generation circuit and having an output coupled to a control input of the demultiplexor.
A multi-channel audio system comprising:
- a bus having a bus data line and a bus clock line;
- a plurality of microphone circuits each having a respective audio pick-up device and a respective bus interface circuit that is coupled to the bus to form a time-division multiplexed multi-drop bus interface arrangement having protocol slots 0, 1, . . . N where N is an integer greater than two;
- and
- a bus device that is to produce a) a frame marker on the bus data line in slot 0, wherein the frame marker has a plurality of framer marker bits each to be driven by the bus device in a respective instance of slot 0, and b) a data bitstream on the bus data line in slot 1,
- wherein the respective bus interface circuit of each of the plurality of microphone circuits is coupled to the bus clock line to receive a clock and to use the clock to detect the frame marker on the bus data line, and in response to having detected the frame marker drive a respective audio bitstream in its assigned protocol slot.
Dependencies are inferred from the claim text.