Bus signal encoded with data and clock signals

A codec, comprising:

• a data and clock encoder that receives bits of data in a first form in which each bit of the data is represented by one of a first logic state and a second logic state and transmits the bits of data serially in a second form in which the first logic state of a bit is represented by maintaining a high voltage and the second logic state of a bit is represented by maintaining a low voltage and an intermediate voltage is maintained between adjacent bits of the bits of data transmitted serially;
• a transmission path coupled to the data and clock encoder that transmits the bits of data in the second form;
• and
• a data and clock decoder coupled to the transmission path that receives the bits of data transmitted in the second form and derives a clock from the intermediate voltage that is maintained between adjacent bits that repetitively:
• is maintained at a logic high;
• then switches directly from the logic high to a logic low,
• then is maintained at the logic low;
• and
• then switches directly between the logic low and the logic high.