Semiconductor Device with IGBT Cell and Desaturation Channel Structure

A semiconductor device, comprising:

• a first IGBT cell comprising a second-type doped drift zone;
• and
• a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell, the desaturation semiconductor structure comprising:
• a first-type doped region forming a pn-junction with the drift zone,
• two portions of a trench or two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction, wherein the two trench portions or the two trenches confine a mesa region comprising a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction, wherein the first-type doping of the desaturation channel region is lower than the first-type doping of the body region, wherein the desaturation channel region is arranged below the body region, and wherein the desaturation channel region and the body region adjoin each other.

A method of operating a semiconductor device comprising a first electrode terminal, a second electrode terminal, a gate electrode terminal, and a first IGBT cell including a gate electrode, a first electrode, a second electrode and a drift region, the gate electrode being connected to the gate electrode terminal, the first electrode is connected to the first electrode terminal, and the second electrode is connected to the second electrode terminal, the semiconductor device further comprising a desaturation semiconductor structure including a desaturation channel, a first portion of the desaturation semiconductor structure being connected to the first electrode terminal and a second portion of the desaturation semiconductor structure is connected to the gate electrode terminal for controlling the desaturation channel, the method comprising:

• applying a gate voltage with a first value to the gate electrode terminal, wherein a current flows through the first IGBT cell between the first electrode terminal and the second electrode terminal and wherein a current flow through the desaturation channel is substantially blocked;
• applying the gate voltage with a second value to the gate electrode terminal, the absolute value of the second value being lower than the absolute value of the first value, wherein a current flows through the first IGBT cell between the first electrode terminal and the second electrode terminal and wherein charge carriers flow as a desaturating current from the drift region of the first IGBT cell through the desaturation channel of the desaturation semiconductor structure to the first electrode terminal;
• and
• applying the gate voltage with a third value to the gate electrode terminal, the absolute value of the third value being lower than the respective absolute values of the first and second values, wherein a current flow through the first IGBT cell between the first electrode terminal and the second electrode terminal is substantially blocked.

A method of forming a bottleneck-type trench structure of a semiconductor device, the method comprising:

• forming a trench in a semiconductor layer having lateral sides and a bottom side;
• introducing a dopant into the bottom side;
• heating the semiconductor device to diffuse the dopant into a diffusion region;
• and
• selectively etching the diffusion region to form the bottleneck-type trench structure.