Circuits and methods for signal interference mitigation

A signal interference mitigation circuit comprising:

• a clock divider circuit configured to generate a first clock signal based on a second clock signal and a division factor pattern, wherein the clock divider circuit comprises:
• a multiplexer circuit configured to receive a selection signal from the control circuit and provide a selection of a division factor based on the division factor pattern and the selection signal;
• a counter configured to receive the selection of the division factor and generate the second clock signal indicative of a count value;
• a first comparator circuit coupled with the counter and the multiplexer circuit, the first comparator circuit configured to compare the selection of the division factor with the count value of the counter at the rate of the generated second clock signal and generate a trigger signal based on the comparison;
• and
• a flip-flop circuit coupled with the first comparator circuit and configured to receive the trigger signal and generate the first clock signal based on the division factor pattern;
• and
• a control circuit coupled with the clock divider circuit, the control circuit configured to:
• determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and
• provide the division factor pattern to the clock divider circuit.

An integrated circuit configured to mitigate signal interference, the integrated circuit comprising:

• a victim circuit operating in a predetermined frequency range;
• an aggressor circuit coupled with the victim circuit and capable of being operated on a first clock signal within the predetermined frequency range of the victim circuit;
• and
• a signal interference mitigation circuit coupled with the aggressor circuit, the signal interference mitigation circuit comprising:
• a clock divider circuit configured to generate the first clock signal, for clocking a digital circuit, based on a division factor pattern and a second clock signal, and
• a control circuit coupled with the clock divider circuit, the control circuit configured to:
• determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and
• provide the division factor pattern to the clock divider circuit.

An integrated circuit configured to mitigate signal interference, the integrated circuit comprising:

• a victim circuit operating in a predetermined frequency range;
• an aggressor circuit coupled with the victim circuit and capable of being operated on a first clock signal within the predetermined frequency range of the victim circuit;
• and
• a signal interference mitigation circuit coupled with the aggressor circuit, the signal interference mitigation circuit comprising:
• a clock divider circuit configured to generate the first clock signal based on a division factor pattern and a second clock signal, wherein the clock divider circuit comprises:
• a multiplexer circuit configured to receive a selection signal from the control circuit and to provide a selection of a division factor based on the division factor pattern and the selection signal;
• a counter configured to receive the selection of the division factor and to generate the second clock signal indicative of a count value;
• a first comparator circuit communicatively associated with the counter and the multiplexer circuit, the first comparator circuit configured to compare the selection of the division factor with the count value of the counter at the rate of the generated second clock signal and generate a trigger signal based on the comparison;
• and
• a flip-flop circuit communicatively associated with the comparator circuit and configured to receive the trigger signal and generate the first clock signal based on the division factor pattern;
• and
• a control circuit coupled with the clock divider circuit, the control circuit configured to:
• determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and
• provide the division factor pattern to the clock divider circuit.

A method for mitigating signal interference of at least one aggressor circuit, the at least one aggressor circuit capable of being operated on a first clock signal in an Integrated Circuit (IC) within an interfering frequency range of at least one victim circuit in the IC, the method at a signal interference mitigation circuit comprising:

• generating a second clock signal;
• determining a division factor pattern for dividing the second clock signal, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, the division factor pattern being determined in a manner so as to control a throughput frequency of the signal interference mitigation circuit;
• and
• generating the first clock signal, for clocking a digital circuit, based on a division of the second clock signal by the plurality of division factors according to the division factor pattern.

A method for mitigating signal interference of at least one aggressor circuit, the at least one aggressor circuit capable of being operated on a first clock signal in an Integrated Circuit (IC) within an interfering frequency range of at least one victim circuit in the IC, the method at a signal interference mitigation circuit comprising:

• generating a second clock signal;
• determining a division factor pattern for dividing the second clock signal, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, the division factor pattern being determined in a manner so as to control a throughput frequency of the signal interference mitigation circuit, wherein determining the division factor pattern comprises:
• generating a plurality of random numbers, by a random number generator, the random number generator being actuated by the first clock signal, wherein each of the plurality of random numbers are updated at a clock edge of the first clock signal;
• comparing the generated random number with a predetermined threshold;
• and
• determining a frequency of occurrence of each division factor from among the plurality of division factors based on comparison;
• and
• generating the first clock signal based on a division of the second clock signal by the plurality of division factors according to the division factor pattern.