Semiconductor Device

A semiconductor device comprising:

• a level shifter;
• a first buffer;
• and
• a second buffer,
• wherein the first buffer comprises a first transistor and a second transistor connected in series,
• wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
• wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
• wherein a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other,
• wherein a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected each other,
• wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, and
• wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
• wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.

A semiconductor device comprising:

• a level shifter;
• a first buffer;
• a second buffer;
• a first switch;
• and
• a second switch;
• wherein the first buffer comprises a first transistor and a second transistor connected in series,
• wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
• wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
• wherein a connection portion of one of a source and a drain of the sixth transistor and one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor via the first switch,
• wherein a connection portion of one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor is electrically connected to a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor via the second switch,
• wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
• wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
• wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.

A semiconductor device comprising:

• a level shifter;
• a first buffer;
• a second buffer;
• a first switch;
• a second switch;
• a first terminal;
• a second terminal configured to receive an inverted signal of a signal input to the first terminal;
• and
• a third terminal configured to receive a clock signal for controlling states of the first switch and the second switch,
• wherein the first buffer comprises a first transistor and a second transistor connected in series,
• wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
• wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
• wherein a connection portion of one of a source and a drain of the sixth transistor and one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor via the first switch,
• wherein a connection portion of one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor is electrically connected to a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor via the second switch,
• wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
• wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
• wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
• wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
• wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.