Non-Volatile Latch Structures with Small Area for FPGA

A latch circuit comprising:

• a first non-volatile tri-gate device coupled between a first node and a bit line;
• a second non-volatile tri-gate device coupled between a second node and source line;
• and
• a cross-coupled circuit coupled to a source of supply voltage and to the first and second nodes.

A method of operating a latch circuit comprising:

• providing a first tri-gate non-volatile device;
• providing a second tri-gate non-volatile device;
• coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device;
• erasing the first tri-gate non-volatile device;
• programming the second tri-gate non-volatile device;
• and
• latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices.