Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit

An integrated circuit, comprising:

• a chip;
• encapsulation material at least partially covering the chip;
• a layer stack disposed at least partially over the encapsulation material, the layer stack comprising:
• a polymer layer disposed over the encapsulation material;
• and
• a metal layer or a ceramic layer disposed over the polymer layer.

An integrated circuit, comprising:

• a carrier;
• a chip mounted on the carrier;
• encapsulation material at least partially covering the chip and the carrier;
• a layer stack disposed over the carrier on a side of the carrier opposite the chip, the layer stack comprising:
• a polymer layer disposed over the carrier;
• and
• a metal layer or a ceramic layer disposed over the polymer layer.

A method for manufacturing an integrated circuit, the method comprising:

• at least partially covering a chip with encapsulation material;
• disposing a layer stack at least partially over the encapsulation material, the layer stack comprising:
• a polymer layer disposed over the encapsulation material;
• and a metal layer or a ceramic layer disposed over the polymer layer.