Trimming circuit for an integrated circuit and related integrated device
AssigneeSTMicroelectronics S.r.l.
InventorGiuseppe Scilla
Life of this patent
Estimating the term…
Abstract
A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation.
Claims12
A trimming circuit configured to carry out a trimming operation on a device portion of an integrated circuit device, comprising:
- a plurality of shunt fuses, each shunt fuse of the plurality of shunt fuses being coupled in parallel to a trimming resistance of a plurality of trimming resistances, and
- a plurality of further resistances, each further resistance of the plurality of the further resistances being coupled in parallel to a respective shunt fuse of the plurality of shunt fuses and configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation.
A semiconductor device, comprising:
- a trimming circuit formed in a semiconductor substrate of a first conductivity type, said trimming circuit comprising:
- a plurality of shunt fuses, each shunt fuse of the plurality of shunt fuses being coupled in parallel to a trimming resistance of a plurality of trimming resistances, and
- a plurality of further resistances, each further resistance of the plurality of the further resistances being coupled in parallel to a respective shunt fuse of the plurality of shunt fuses and configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation;
- wherein said pluralities of shunt fuses and further resistances are formed of:
- a highly-doped layer of a second conductivity type placed over said substrate,
- a first insulating layer placed selectively over said highly-doped layer of the second conductivity type to form a plurality of regions of insulating layer and a plurality of contact zones wherein no insulating layer is present so that each region of insulating layer is comprised between two adjacent contact zones, and
- a metal layer placed over said first insulating layer and in the contact zones to contact the highly-doped layer of a second conductivity type so that each further resistance of the plurality of further resistances is formed of each portion of said highly-doped layer of a second conductivity type comprises between two adjacent contact zones and under the region of the insulating layer comprised between said two adjacent contact zones and the respective shunt fuse of the plurality of shunt fuses is formed of the portion of said metal layer placed over said region of the insulating layer comprised between said two adjacent contact zones.
A method for manufacturing a semiconductor, comprising:
- forming a highly-doped layer of a second conductivity type over a semiconductor substrate of a first conductivity type,
- forming an insulating layer over the highly-doped layer of the second conductivity type,
- selectively removing the insulating layer to form a plurality of insulating layer regions and a plurality of contact zones wherein no insulating layer is present so that each region of insulating layer is comprised between two adjacent contact zones,
- forming a first metal layer over the insulating layer and in the contact zones to contact the highly-doped layer of a second conductivity type so as to form:
- a resistance comprising a portion of said highly-doped layer of a second conductivity type between two adjacent contact zones and under the region of the insulating layer comprised between said two adjacent contact zones and
- a shunt fuse formed of the portion of said metal layer placed over said region of the insulating layer between said two adjacent contact zones.
Dependencies are inferred from the claim text.