Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts

A method for fabricating an integrated circuit comprising:

• forming over a semiconductor substrate a gate structure;
• forming a conformal spacer around the gate structure;
• performing an ion implantation into the semiconductor substrate using the conformal spacer as a mask;
• and
• removing the conformal spacer;
• depositing a non-conformal spacer material around the gate structure;
• etching the non-conformal spacer material to form a salicidation spacer;
• and
• forming a self-aligned silicide contact adjacent the salicidation spacer.

An integrated circuit comprising:

• a gate structure formed on a semiconductor substrate and including a high-k dielectric layer, a metal electrode formed over the high-k dielectric layer, a gate cap formed over the metal electrode, and an electrode adjacent spacer formed around the gate cap and metal electrode;
• a salicidation spacer formed around the gate structure;
• a source/drain extension region formed in the semiconductor substrate and aligned with the electrode adjacent spacer;
• a self-aligned silicide contact formed in the semiconductor substrate adjacent the salicidation spacer;
• and
• a deep source/drain region formed in the semiconductor substrate in non-alignment with the silicidation spacer.