US 2014/0197497 A1 · NATIVE PMOS DEVICE WITH LOW THRESHOLD VOLTAGE AND HIGH DRIVE CURRENT AND METHOD OF FABRICATING THE SAME

Abstract

A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

Claims23

Dependent claims

A P-type metal-oxide semiconductor (PMOS) device, comprising:

a substrate having a first material;
a source region having a second material configured to provide a first strained region;
a drain region having the second material configured to provide a second strained region;
and
a gate region between the source region and the drain region, the gate region comprising:
a first layer having a first thickness;
a second layer having a second thickness, the second thickness being greater than the first thickness;
and
a third layer having a third thickness, the third thickness being greater than the second thickness.

6 more elements

A P-type metal oxide semiconductor (PMOS) device, comprising:

a substrate having a first material,
a source region having a first raised region, a top side of the first raised region being raised above a top side of the substrate,
a drain region having a second raised region, a top side of the second raised region being raised above the top side of the substrate,
a gate region between the source region and drain region, the gate region comprising:
a first layer having a first thickness;
a second layer having a second thickness, the second thickness being greater than the first thickness;
and
a third layer having a third thickness, the third thickness being greater than the second thickness.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/741,157Filed 14 Jan 2013

Published

17 Jul 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain

Native pmos device with low threshold voltage and high drive current and method of fabricating the same

Life of this patent

Native pmos device with low threshold voltage and high drive current and method of fabricating the same

Life of this patent

Abstract

Claims23