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US 2014/0197496 A1Published application
Semiconductor Structure with Suppressed STI Dishing Effect at Resistor Region
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHarry-Hak-Lay Chuang, Ming Zhu, Lee-Wee Teo, Bao-Ru Young
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Abstract
An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.
Claims20
An integrated circuit, comprising:
- a semiconductor substrate;
- and
- a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, wherein the first width is less than the second width, and the first STI feature has an etch-resistance less than that of the second STI feature.
An integrated circuit, comprising:
- a semiconductor substrate;
- a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, the first width being substantially less than the second width;
- a first field-effect transistor (FET) disposed in a first active region of the semiconductor substrate;
- and
- a plurality of resistors disposed on the second STI feature and spaced away from each other within the second width,
- wherein the first STI feature includes an impurity and has an etch-resistance less than that of the second STI feature.
3 more elements
An integrated circuit, comprising:
- a semiconductor substrate;
- a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, the first width being substantially less than the second width;
- a first resistor disposed on the second STI feature;
- a first field-effect transistor (FET) for an input/output (I/O) circuit disposed in a first active region of the semiconductor substrate, the first FET including a first gate oxide layer of a first thickness;
- and
- a second FET disposed in a second active region of the semiconductor substrate, the second FET including a second gate oxide layer of a second thickness substantially less than the first thickness.
3 more elements
Dependencies are inferred from the claim text.