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US 2014/0197495 A1Published application
Semiconductor device and method of forming the same
AssigneeElpida Memory, Inc.
InventorYoshikazu MORIWAKI
Life of this patent
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Abstract
A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
Claims8
A semiconductor device comprising:
- an n-MOS transistor;
- and
- a p-MOS transistor that comprises a gate insulating film and a gate electrode, the gate electrode having an adjacent portion that is adjacent to the gate insulating film, the adjacent portion comprising a polysilicon that contains an n-type dopant and a p-type dopant.
A method of forming a semiconductor device comprising an n-MOS transistor and a p-MOS transistor, the method comprising:
- forming a gate insulating film over an n-MOS transistor region and a p-MOS transistor region of a semiconductor substrate;
- forming a first polysilicon layer over the gate insulating film, the first polysilicon layer containing an n-type dopant;
- forming a second polysilicon layer over the first polysilicon layer, the second polysilicon layer being substantially free of any dopant;
- patterning the stack of the first and second polysilicon layers to form gate electrode structures in the n-MOS transistor region and the p-MOS transistor region;
- carrying out a first ion-implantation process of an n-type dopant to the n-MOS transistor region, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the n-MOS transistor region;
- and
- carrying out a second ion-implantation process of a p-type dopant to the p-MOS transistor region, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.
4 more elements
Dependencies are inferred from the claim text.