Semiconductor device and manufacturing method thereof
AssigneeFuji Electric Co., Ltd.
InventorMasaharu YAMAJI
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AssigneeFuji Electric Co., Ltd.
InventorMasaharu YAMAJI
Estimating the term…
A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method of manufacturing a semiconductor device including a first conductivity type well layer and second conductivity type well layer disposed on a first conductivity type semiconductor substrate and a first conductivity type second well layer selectively disposed in a surface layer of the second conductivity type well layer, the manufacturing method comprising:
Dependencies are inferred from the claim text.