Semiconductor structure having common gate and fabrication method thereof

A method for forming a semiconductor structure having a common gate, comprising:

• providing a semiconductor substrate having a first transistor region, a second transistor region, and an isolation structure in the semiconductor substrate formed between the first transistor region and the second transistor region;
• forming a dummy gate structure on each surface of the first transistor region, the second transistor region, and the isolation structure of the semiconductor substrate;
• forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer has a top surface leveled with the dummy gate structure;
• etching a first portion of the dummy gate structure corresponding to the first transistor region to form a first trench, and forming a first high-K gate dielectric layer on an inner wall of the first trench, and forming a first metal gate electrode on the first high-K gate dielectric layer, to form a first metal gate;
• etching a second portion of the dummy gate structure corresponding to the second transistor region to form a second trench, and forming a second high-K gate dielectric layer on an inner wall of the second trench, and forming a second metal gate electrode on the second high-K gate dielectric layer, to form a second metal gate, wherein the first metal gate and the second metal gate have a boundary located on the surface of the isolation structure;
• forming a third trench over the isolation structure by etching at least a portion of the first metal gate and a portion of the second metal gate at the boundary;
• and
• forming a conductive material layer in the third trench over the isolation structure and connecting the first metal gate electrode of the first metal gate with the second metal gate electrode of the second metal gate.