Semiconductor Structure Including A Spatially Confined Dielectric Region

A semiconductor structure comprising:

• a III-Nitride field-effect transistor (FET) including a drain, a source, and a gate, fabricated over a substrate;
• a spatially confined dielectric region formed under each of said source and said drain in said substrate;
• said spatially confined dielectric region reducing a capacitive coupling of said source and said drain to said substrate.

A method comprising:

• forming a spatially confined dielectric region in a substrate;
• fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
• said drain of said III-Nitride FET being formed over said spatially confined dielectric region so as to reduce a capacitive coupling of said drain to said substrate.

A method comprising:

• forming spatially confined dielectric regions in a substrate;
• fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
• each of said drain and said source of said III-Nitride FET being formed over a respective one of said spatially confined dielectric regions so as to reduce a capacitive coupling of said drain and said source to said substrate.