Cmos nanowire structure

A semiconductor structure, comprising:

• a first semiconductor device comprising:
• a first nanowire disposed above a substrate, the first nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region, the discrete channel region comprising a semiconductor backbone material;
• and
• a first gate electrode stack completely surrounding the discrete channel region of the first nanowire;
• and
• a second semiconductor device comprising:
• a second nanowire disposed above the substrate, the second nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region, the discrete channel region comprising the semiconductor backbone material as well as a surrounding cladding material layer not included in the channel region of the first semiconductor device;
• and
• a second gate electrode stack completely surrounding the discrete channel region of the second nanowire.

A method of fabricating a CMOS nanowire semiconductor structure, the method comprising:

• forming a first active layer above a substrate, the first active layer having a first lattice constant;
• forming a second active layer on the first active layer, the second active layer having a second lattice constant greater than the first lattice constant;
• forming, from the first active layer, a first nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region;
• forming, from the second active layer, a second nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region;
• forming a first gate electrode stack completely surrounding the discrete channel region of the first nanowire;
• and
• forming a second gate electrode stack completely surrounding the discrete channel region of the second nanowire.