System and method for re-factorizing a square matrix into lower and upper triangular matrices on a parallel processor

A SIMD processor, comprising:

• lanes operable to process parallel threads;
• a pipeline control unit system operable to control thread processing in said lanes;
• and
• a system for employing said lanes and said pipeline control unit to re-factorize a square input matrix, including:
• a matrix generator operable to generate an intermediate matrix by embedding a permuted form of said input matrix in a zeroed-out sparsity pattern of a combination of lower and upper triangular matrices resulting from an LU factorization of a previous matrix having a same sparsity pattern, reordering to minimize fill-in and pivoting strategy as said input matrix, and
• a re-factorizer associated with said matrix generator and operable to transmit parallel threads to said pipeline control unit to apply an incomplete-LU factorization with zero fill-in on said intermediate matrix.