Memory testing with selective use of an error correction code decoder
AssigneeInternational Business Machines Corporation
InventorsMarc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
Life of this patent
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Abstract
A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.
Claims20
A method comprising:
- in response to receiving a test activation request indicating a memory location of
- a memory device:
- directing an access of the memory location to an error correction code (ECC) decoder;
- writing a test pattern to the memory location;
- reading a value from the memory location;
- and
- determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.
A system comprising:
- a rank including a dynamic random-access memory (DRAM);
- an error correction code (ECC) decoder configured to:
- detect an error at a memory location of the DRAM;
- and
- in response to detecting the error, place a chip mark associated with the DRAM;
- firmware configured to:
- detect the chip mark associated with the DRAM;
- direct an access of the DRAM to the ECC decoder while the chip mark associated with the DRAM is in place;
- and
- request a self-test engine to perform a test of the memory location;
- and
- the self-test engine configured to:
- write to the rank including writing a test pattern to the memory location;
- read from the rank including reading a value from the memory location;
- and
- determine whether a fault is detected at the memory location based on a comparison of the value and the test pattern.
A computer-readable medium storing instructions that, when executed by a processor, cause the processor to:
- in response to receiving a test activation request indicating a memory location:
- direct an access of the memory location to an error correction code (ECC) decoder;
- write a test pattern to the memory location;
- read a value from the memory location;
- and
- determine whether a fault is detected at the memory location based on a comparison of the test pattern and the value.
Dependencies are inferred from the claim text.