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US 2014/0195852 A1Published application
Memory testing of three dimensional (3d) stacked memory
AssigneeInternational Business Machines Corporation
InventorsMarc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
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Abstract
A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer.
Claims20
A method comprising:
- reading, at a memory controller, first data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack comprising a plurality of stacked DRAM die layers;
- writing the first data to a second DRAM die layer of the DRAM stack;
- and
- after writing the first data to the second DRAM die layer, sending a first request to a test engine to test the first DRAM die layer.
1 more element
An apparatus comprising:
- a dynamic random-access memory (DRAM) stack that includes:
- a first DRAM die layer;
- and
- a logic DRAM die layer comprising logic configured to:
- receive a request to test the first DRAM die layer;
- perform testing of the first DRAM die layer in response to the request;
- and
- generate a result of testing the first DRAM die layer, wherein the result indicates whether a fault was detected at the first DRAM die layer.
5 more elements
A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to:
- read first data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack comprising a plurality of stacked DRAM die layers;
- write the first data to a second DRAM die layer of the DRAM stack;
- and
- after writing the first data to the second DRAM die layer, send a first request to a test engine to test the first DRAM die layer.
1 more element
Dependencies are inferred from the claim text.