System and method for providing power savings in a processor environment

An apparatus for reducing power consumption in a processing environment, comprising:

• a central processing unit (CPU);
• and
• a root port configured to be powering down, wherein the CPU is configured to initiate a first downstream cycle to the root port and to receive a power up indicator, and wherein an exit flow is to be triggered for a power state in conjunction with sending a second downstream cycle to the root port.

A method for reducing power consumption in a processing environment, comprising:

• identifying a power management state associated with a central processing unit (CPU);
• applying a power down state through a common mode turn off;
• applying a transmit (Tx) common mode disable pin to a physical layer (PHY) in order to change a power state level associated with the CPU.

An apparatus for reducing power consumption in a processing environment, comprising:

• a central processing unit (CPU);
• and
• a root port coupled to the CPU, wherein a power management state associated with a central processing unit (CPU) is identified, and wherein a power down state is applied through a common mode turn off, and wherein a transmit (Tx) common mode disable pin is applied to a physical layer (PHY) in order to change a power state level associated with the CPU.