System and method for power management

A system, comprising:

• a processor;
• and
• a memory to store instructions that when executed by the processor performs operations, comprising:
• identifying a power management event (PME) timeout;
• directing a receiver in a physical layer (PHY) to turn off;
• transitioning from a powered-on link state to a recovery state;
• and
• resuming a detection state associated with a predetermined timeout associated with failing to receive a sequence from the electronic device.

A system, comprising:

• a processor;
• and
• a memory to store instructions that when executed by the processor performs operations, comprising:
• providing a configuration bit of a root port;
• initiating a power management event turn off/acknowledgment handshake signal for the root port for putting a corresponding link into layer 2/layer 3 (L2/L3) ready state;
• instructing a power management controller (PMC) to assert a reset for the electronic device;
• and
• removing power such that the electronic device transitions to a cold state.

An apparatus to manage power for at least one processor, comprising:

• logic, the logic at least partially including hardware logic, to:
• evaluate a plurality of ports associated with an electronic device;
• determine that a particular pin associated with at least one of the plurality of the ports is not receiving a signal;
• disable a squelch function associated with the electronic device;
• and
• gate power associated with a physical layer (PHY) of the electronic device.