Microprocessor that facilitates task switching between encrypted and unencrypted programs

A method for operating a microprocessor having an instruction cache and an architected register, the method comprising:

• setting a bit in the architected register and then fetching encrypted instructions from the instruction cache and decrypting them prior to executing them;
• saving the value of the bit in the architected register and then clearing the bit, in response to receiving an interrupt;
• fetching unencrypted instructions from the instruction cache and executing them without decrypting them, after said clearing the bit;
• restoring the saved value to the bit in the architected register, in response to executing a return from interrupt instruction;
• and
• resuming said fetching and decrypting and executing the encrypted instructions, in response to determining that the restored value of the bit is set.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising:
• first program code for specifying an architected register, having a bit, wherein the microprocessor is configured to set the bit;
• and
• second program code for specifying a fetch unit, configured to fetch encrypted instructions from an instruction cache and decrypt them prior to executing them, in response to the microprocessor setting the bit;
• wherein the microprocessor is configured to save the value of the bit to a stack in memory and then clear the bit, in response to receiving an interrupt;
• wherein the fetch unit is configured to fetch unencrypted instructions from the instruction cache and execute them without decrypting them, after the microprocessor clears the bit;
• wherein the microprocessor is configured to restore the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction;
• and
• wherein the fetch unit is configured to resume fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set.