Three input operand vector add instruction that does not raise arithmetic flags for cryptographic applications

An apparatus, comprising:

• an instruction execution pipeline implemented on a semiconductor chip comprising:
• an execution unit having logic circuitry to:
• sum three input vector operands through execution of a single instruction;
• and,
• not raise any arithmetic flags even though a result of said sum creates more bits than circuitry designed to transport said sum is able to transport.

A machine readable medium containing program code that when processed by a digital processing system causes a method to be performed, said method, comprising:

• compiling program code to create a flow of instructions to perform a round of an encryption process, said flow of instructions including:
• a first instruction that performs a logic function on three input vector operands, said first instruction also having an input operand that specifies which of a plurality of possible logic functions is to be performed on said three input vector operands;
• and,
• second and third instructions that each perform a summation on their own respective three input vector operands, wherein both said second and third instructions will not raise an arithmetic flag upon a carry out or overflow condition.

A machine readable medium containing program code that when processed by a digital processing system causes a method to be performed, said method comprising:

• performing a round of an encryption process by performing the following:
• executing a first instruction that performs a logic function on three input vector operands, said first instruction also having an input operand that specifies which of a plurality of possible logic functions is to be performed on said three input vector operands;
• and,
• executing second and third instructions that each perform a summation on their own respective three input vector operands, both said second and third instructions not raising an arithmetic flag upon a carry out or overflow condition, a result of said second instruction also being an input vector operand for said third instruction.