Formal verification of a logic design

A computer system for formal verification of a logic design for a processor execution unit, the processor execution unit comprising an instruction pipeline with one or more pipeline stages for executing a plurality of instructions, the computer system comprising:

• a memory;
• and
• a processor in communications with the memory, wherein the computer system is configured to perform a method, the method comprising:
• creating a design under test by using at least a first and a second instance of the logic design;
• initializing the instruction pipeline using the first instance of the design under test with a defined initial value in each instruction pipeline stage and the second instance with random initial values in its pipeline stages;
• selecting an instruction of the processor execution unit out of the plurality of instructions and simultaneously issuing the instruction to each instance of the design under test;
• providing a comparison result between the outputs of the instruction pipeline executing the instruction for each instance;
• and
• in case the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true, or in case the instruction is not verifiable by formal model checking, approving the correctness of the sequenced computation in the instruction pipeline, if the comparison result is true.

A computer program product comprising:

• a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
• creating a design under test by using at least a first and a second instance of the logic design;
• initializing the instruction pipeline using the first instance of the design under test with a defined initial value in each instruction pipeline stage and the second instance with random initial values in its pipeline stages;
• selecting an instruction of the processor execution unit out of the plurality of instructions and simultaneously issuing the instruction to each instance of the design under test;
• providing a comparison result between the outputs of the instruction pipeline executing the instruction for each instance;
• and
• in case the instruction is verifiable by formal model checking, approving the correctness of the logic design, if the comparison result is true, or in case the instruction is not verifiable by formal model checking, approving the correctness of the sequenced computation in the instruction pipeline, if the comparison result is true.