Method, device and system for controlling execution of an instruction sequence in a data stream accelerator
AssigneeIntel Corporation
InventorVladimir Ivanov
Life of this patent
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Abstract
Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data stream processing engine detects that execution of a first instruction in an instruction sequence has ended. In another embodiment, the control unit determines information regarding a next instruction of the instruction sequence which is to be executed. Control signals may be sent from the control unit to form a data path set for execution of the next instruction in the instruction sequence.
Claims24
An integrated circuit for operation in a data stream processing engine (DSPE) of an accelerator, the integrated circuit comprising:
- an instruction sequencer to detect a first control signal sent from a data path module of the DSPE to the integrated circuit, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for a data processing task, the first instruction to perform multiple atomic operations;
- and
- a control signal generator coupled to receive instruction information sent from the instruction sequencer in response to the first control signal, the instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations, the control signal generator to send to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for multiple data processing units (DPUs) of the data path module to form a set of one or more data paths corresponding to the second instruction.
A method at a control unit in a data stream processing engine (DSPE) of an accelerator, the method comprising:
- detecting a first control signal sent from a data path module of the DSPE, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for a data processing task, the first instruction to perform multiple atomic operations;
- in response to the first control signal, providing instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations;
- sending to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for multiple data processing units (DPUs) of the data path module to form a set of one or more data paths corresponding to the second instruction.
A computer platform comprising:
- a processor;
- an accelerator coupled to the processor, the accelerator to perform a data processing task for the processor, the accelerator including:
- a data path module including multiple data processing units (DPUs);
- and
- a control unit including:
- an instruction sequencer to detect a first control signal sent from the data path module, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for the data processing task, the first instruction to perform multiple atomic operations;
- and
- a control signal generator coupled to receive instruction information sent from the instruction sequencer in response to the first control signal, the instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations, the control signal generator to send to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for the multiple DPUs to form a set of one or more data paths corresponding to the second instruction;
- and
- a network interface coupled to the processor, the network interface to couple the computer platform to a network.
Dependencies are inferred from the claim text.