Variable depth instruction fifos to implement simd architecture

An apparatus, comprising:

• a plurality of variable depth instruction FIFOs and a plurality of data caches created from a plurality of caches corresponding to a plurality of processors, including a first variable depth instruction FIFO, a second variable depth instruction FIFO, and a third variable depth instruction FIFO, and wherein the plurality of caches and the plurality of processors correspond to MIMD architecture;
• the first variable depth instruction FIFO configured to cascade an instruction within the first variable depth instruction FIFO and to cascade the instruction to the second variable depth instruction FIFO to implement SIMD architecture;
• and
• the second variable depth instruction FIFO configured to cascade the instruction within the second variable depth instruction FIFO and to cascade the instruction to a third variable depth instruction FIFO to implement SIMD architecture.