Apparatus and method for sliding window data access
AssigneeIntel Corporation
InventorAshish Jha
Life of this patent
Estimating the term…
Abstract
An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers.
Claims31
A processor to execute an instruction to perform the operations of:
- determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
- determining the system memory addresses for each of the N designated portions of the data stream;
- fetching the N designated portions of the data stream from the system memory at the system memory addresses;
- and
- storing the N designated portions of the data stream into the N vector registers.
A method comprising:
- determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
- determining the system memory addresses for each of the N designated portions of the data stream;
- fetching the N designated portions of the data stream from the system memory at the system memory addresses;
- and
- storing the N designated portions of the data stream into the N vector registers.
A computer system comprising:
- a memory for storing program instructions and data;
- a processor to execute one or more of the program instructions to perform the operations of:
- determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
- determining the system memory addresses for each of the N designated portions of the data stream;
- fetching the N designated portions of the data stream from the system memory at the system memory addresses;
- and
- storing the N designated portions of the data stream into the N vector registers.
A processor to execute an instruction comprising:
- means for determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory;
- means for determining the system memory addresses for each of the N designated portions of the data stream;
- means for fetching the N designated portions of the data stream from the system memory at the system memory addresses;
- and
- means for storing the N designated portions of the data stream into the N vector registers.
-39. (canceled)
Dependencies are inferred from the claim text.