Line termination methods and apparatus

A method of terminating a plurality of conductors in a memory system comprising one or more memory devices coupled to the plurality of conductors, the method comprising:

• receiving a selected address at each of the one or more memory devices;
• and
• selecting termination circuitry in a particular memory device responsive to receiving the selected address;
• wherein the termination circuitry is configured to adjust an impedance characteristic of the particular memory device.

A method of operating one or more memory devices commonly coupled by an address bus and a data bus, the method comprising:

• selecting termination circuitry in a particular number of the one or more memory devices responsive to the particular number of memory devices receiving an indication that a particular memory device of the one or more memory devices is selected for a memory device operation;
• wherein each of the particular number of memory devices comprises one or more die each die having associated termination circuitry;
• and
• wherein the termination circuitry associated with each die is configured to adjust an impedance characteristic of one or more data nodes coupled to the data bus of each die's respective memory device;
• and
• wherein the termination circuitry associated with each die is further configured to be adjusted independently of each other die.

A memory device, comprising:

• an interface comprising one or more nodes;
• one or more termination circuits, where each termination circuit is configured to adjust an impedance characteristic of a respective one of the nodes of the interface;
• an array of memory cells;
• and
• control circuitry, wherein the control circuitry is configured to activate the one or more termination circuits responsive to a particular address received at the interface.