System and method for out-of-order prefetch instructions in an in-order pipeline
AssigneeIntel Corporation
InventorJames Earl McCormick, JR.
Life of this patent
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AssigneeIntel Corporation
InventorJames Earl McCormick, JR.
Estimating the term…
Apparatuses, systems, and a method for providing a processor architecture with data prefetching are described. In one embodiment, a system includes one or more processing units that include a first type of in-order pipeline to receive at least one data prefetch instruction. The one or more processing units include a second type of in-order pipeline having issues slots to receive instructions and a data prefetch queue to receive the at least one data prefetch instruction. The data prefetch queue may issue the at least one data prefetch instruction to the second type of in-order pipeline based upon one or more factors (e.g., at least one execution slot of the second type of in-order pipeline being available, priority of the data prefetch instruction).
A processor architecture, comprising:
A system, comprising:
A computer-implemented method, comprising:
A machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising:
Dependencies are inferred from the claim text.