Memory device having an adaptable number of open rows

A method of opening rows in a memory device, the memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the method comprising the operations of:

• (a) receiving a first command to open a row, the command including a selected row address and a row mode indicator specifying a number of rows to open starting from the selected row address;
• (b) loading the selected row address into at least one row address buffer;
• (c) decoding the selected row address to access a selected row in the memory array using a row decoder;
• (d) reading the selected row and transmitting content of the selected row to a corresponding row data buffer of a set of row data buffers using an array of sense amplifiers;
• and
• if the specified number of rows to open is greater than one,
• then:
• (e) computing a successive selected row address based on the selected row address;
• and
• (f) repeating operations (b), (c), and (d) with the selected row address being replaced by the successive selected row address.

A memory controller for accessing a memory device, the memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the memory device being capable of having an adaptable number of open rows, the memory controller comprising:

• an arbiter for receiving and scheduling a memory access request from a requestor, the memory access request including a logical address, the arbiter being configured to determine the adaptable number of open rows for the memory access request;
• a memory mapper coupled to the arbiter for translating the logical address into a physical address including a row address and a column address;
• and
• a command generator coupled to the memory mapper and the arbiter for generating a sequence of commands corresponding to the memory access request and for sending the sequence of commands to the memory device, one command of the sequence of commands including a row mode indicator specifying the adaptable number of open rows.

A system comprising:

• a memory device including a memory array comprising data elements organized into rows and columns, each of the rows being addressable by a row address, each of the data elements in each of the rows being addressable by a column address, the memory device being capable of having an adaptable number of open rows, the memory device comprising a set of row data buffers for holding contents of the adaptable number of open rows;
• a memory controller configured to receive memory access requests from a requestor and coupled to the memory device for accessing the memory device;
• and
• a processor coupled to the memory controller, the processor being capable of executing a row determination module included in the processor;
• wherein the adaptable number of open rows is determined either by the memory controller from monitoring memory access pattern of the requestor or by the processor from executing the row determination module.