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US 2014/0195758 A1Published application
Block or page lock features in serial interface memory
AssigneeMicron Technology, Inc.
InventorTheodore T. Pekny
Life of this patent
Estimating the term…
Abstract
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.
Claims23
A memory device comprising:
- a memory array;
- a serial interface controller having a serial data in (SI) input configured to receive a signal from a master device;
- and
- a register coupled to the serial interface controller, wherein the register is configured to enable or disable access to a portion of the memory array when data indicating whether to enable or disable access to the portion is written into the register via the SI input.
1 more element
A system comprising:
- a master device;
- and
- a memory device, the memory device comprising:
- a memory array;
- a serial interface controller having a serial data in (SI) input configured to receive a signal from the master device;
- a register communicably coupled to the serial interface controller and configured to enable or disable access to a portion of the memory array responsive to a command addressing the portion and data indicating whether to enable or disable access to the portion, wherein the command addressing the portion and the data are serially received on the SI input from the master device.
3 more elements
A system comprising:
- a master device;
- and
- a plurality of memory devices coupled to the master device, wherein each memory device of the plurality of memory devices comprises:
- a memory array;
- a serial interface controller having a serial data in (SI) input configured to receive a signal from the master device;
- a register communicably coupled to the serial interface controller and configured to enable or disable access to a portion of the memory array responsive to a command addressing the portion and data indicating whether to enable or disable access to the portion, wherein the command addressing the portion and the data are serially received on the SI input from the master device.
3 more elements
Dependencies are inferred from the claim text.