On-chip traffic prioritization in memory

A memory system, comprising:

• a processing element coupled to a crossbar interconnect of a memory device and one or more other processing elements coupled to the crossbar interconnect of the memory device, the processing element configured to send a memory access request comprising a priority value to the crossbar interconnect;
• and
• the memory device comprising:
• a plurality of memory controllers;
• a vault of stacked memory coupled to each of the plurality of memory controllers;
• the crossbar interconnect configured to route the memory access request to a memory controller of the plurality of memory controllers associated with the memory access request;
• and
• the memory controller associated with the memory access request comprising a queue and configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request, the plurality of memory access requests from the processing element and the one or more other processing elements.