US 2014/0195743 A1 · ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY

Abstract

According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Claims21

Dependent claims

A method for traffic prioritization in a memory device, the method comprising:

sending a memory access request comprising a priority value from a processing element in the memory device to a crossbar interconnect in the memory device;
routing the memory access request through the crossbar interconnect to a memory controller in the memory device associated with the memory access request;
receiving the memory access request at the memory controller;
comparing the priority value of the memory access request to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request;
and
performing a next memory access request by the memory controller based on the highest priority memory access request.

3 more elements

A method for traffic prioritization in a memory system, the method comprising:

sending a memory access request comprising a priority value from a processing element to a crossbar interconnect in a memory device;
routing the memory access request through the crossbar interconnect to a memory controller in the memory device associated with the memory access request;
receiving the memory access request at the memory controller to access memory in a vault of stacked memory chips controlled by the memory controller;
comparing the priority value of the memory access request to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request, the plurality of memory access requests from the processing element and one or more other processing elements;
and
performing a next memory access request by the memory controller based on the highest priority memory access request.

3 more elements

Dependencies are inferred from the claim text.

On-chip traffic prioritization in memory

Life of this patent

On-chip traffic prioritization in memory

Life of this patent

Abstract

Claims21