System on chip including memory management unit and memory address translation method thereof

A system on chip (SoC) comprising:

• a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets;
• a memory management unit (MMU) module comprising a plurality of MMUs, each of which is allocated for one of the working sets and is configured to translate virtual addresses corresponding to the request into physical addresses;
• a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the plurality of MMUs, to the memory device;
• and
• a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the plurality of working sets.

A memory address translation method comprising:

• outputting a request for each of a plurality of working sets, which are processed by a master intellectual property (IP), using the master IP;
• allocating one of a plurality of memory management units (MMUs) for each working set;
• translating virtual addresses corresponding to the request into physical addresses using the allocated MMU;
• and
• transmitting the address-translated request to the physical addresses of a memory device.

An electronic system comprising:

• a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets;
• a memory management unit (MMU) module including a plurality of MMUs, each of which is allocated for one of the plurality of working sets and is configured to translate virtual addresses corresponding to the request into physical addresses;
• a memory device configured to process each request of the master IP and to transmit a response or data corresponding to the request;
• a first bus interconnect configured to connect the MMU module with the memory device, configured to transmit each request of the plurality of MMUs to the memory device, and configured to transmit the response or the data corresponding to the request processed by the memory device to the MMU module;
• and
• a second bus interconnect configured to,
• connect the master IP with the MMU module,
• allocate one of the plurality of MMUs for each of the working sets,
• transfer each request of the master IP to the allocated MMU, and
• transmit the response or the data from the allocated MMU to the master IP.

A system on chip (SoC) comprising:

• a master intellectual property (IP) configured to output one or more requests corresponding to a first working set of data and a second working set of data;
• and
• a memory management unit (MMU) module including,
• a first MMU configured to perform a first translation operation including translating a virtual address of the first working set of data into a physical address, and
• a second MMU configured to perform a second translation operation including translating a virtual address of the second working set of data into a physical address,
• wherein the MMU module is configured such that the first and second MMUs are different units and the first and second translation operations are performed by the first and second MMUs simultaneously.