Flush Engine

A method, comprising:

• copying, by a hardware flush unit, modified data from a first cache to a second cache in response to an indication to put the first cache into a low-power state;
• and
• putting the first cache into a low-power state after said copying;
• wherein the first cache is at a lower-level in a memory hierarchy than the second cache.

A processor, comprising:

• a lower-level cache and a higher-level cache;
• and
• a hardware flush unit configured to copy data from the lower-level cache to the higher-level cache in response to an indication that the lower-level cache is to enter a low-power state;
• wherein the processor is configured to put the lower-level cache into a low-power state after the hardware flush unit has copied the data.

A method, comprising:

• flushing first data from a first cache to a second cache in response to determining that a processing element has entered a memory quiescent state;
• causing the first cache to enter a low-power state;
• flushing second data from the second cache in response to an end of a particular time interval from the flushing the first data;
• and
• causing the second cache to enter a low-power state.

A processor core, comprising:

• an instruction fetch unit;
• an L1 data cache;
• an L2 data cache;
• and
• a flush engine configured to:
• determine that the processor core has reached a memory quiescent state;
• copy modified data from the L1 data cache to the L2 data cache;
• wait a particular time interval after determining that the processor has reached a memory quiescent state;
• after waiting the particular time interval, copy data from the L2 data cache to a higher-level cache or to a memory.