Memory Using Voltage to Improve Reliability for Certain Data Types
AssigneeFreescale Semiconductor, Inc.
InventorsAndrew C. Russell, Ravindraraj Ramaraju
Life of this patent
Estimating the term…
Abstract
A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.
Claims20
A memory system comprising:
- a memory array, the memory array comprising a plurality of sections, each of the plurality of sections being individually configurable to operate in a more error resistant mode of operation and a less error resistant mode of operation;
- and,
- a memory controller, the memory controller determining whether data to be written to the memory array comprises modified information, the memory controller storing the modified information to a section operating in the more error resistant mode of operation.
A method for improving error resilience in a memory array comprising a plurality of sections comprising:
- storing modified information to one of the plurality of sections;
- individually configuring each of the plurality of sections to operate in a more error resistant mode of operation and a less error resistant mode of operation;
- determining whether data to be written to the memory array comprises modified information;
- storing the modified information to a section operating in the more error resistant mode of operation.
A memory comprising:
- a first plurality of bitcells and a second plurality of bitcells, each of the first plurality of bitcells and the second plurality of bitcells being individually configurable to operate in a more error resistant mode of operation and a less error resistant mode of operation;
- storing modified data only in the more error resistant plurality of bitcells.
The memory of claim 21 wherein the voltage across the first plurality of bitcells is greater than the voltage across the second plurality of bitcells.
Dependencies are inferred from the claim text.