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US 2014/0195729 A1Published application
Memory Having Improved Reliability for Certain Data Types
AssigneeFreescale Semiconductor, Inc.
InventorsAndrew C. Russell, Ravindraraj Ramaraju
Life of this patent
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Abstract
A method for minimizing soft error rates within caches by configuring a cache with certain sections to correspond to bitcell topologies that are more resistant to soft errors and then using these sections to store modified data.
Claims22
A cache system comprising:
- a cache array, the cache array comprising a plurality of sections, at least one of the sections comprising bitcells configured with an error resistant bitcell topology and at least another of the sections comprising bitcells configured with a less error resistant bitcell topology;
- and,
- cache control logic, the cache control logic determining whether information to be written to the cache array comprises modified information, the cache control logic storing the modified information to the at least one of the sections comprising the cells configured with the error resistant bitcell topology.
A method for improving error resilience comprising:
- providing a cache array, the cache array comprising a plurality of sections, at least one of the sections comprising bitcells configured with an error resistant bitcell topology at least another of the sections comprising bitcells configured with a less error resistant bitcell topology;
- determining whether data to be written to the cache array comprises modified information;
- and,
- storing the modified information to the at least one of the sections configured via the error resistant bitcell topology.
1 more element
A memory comprising:
- a first plurality of bitcells and a second plurality of bitcells, the first plurality of bitcells comprising bitcells having an error resistant topology and the second plurality of bitcells comprising bitcells having to another topology;
- a controller, the controller storing modified data only in the first plurality of bitcells.
Dependencies are inferred from the claim text.