Controller, data storage device and data storage system having the controller, and data processing method
AssigneeSamsung Electronics Co., Ltd.
InventorTae Hack LEE
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Abstract
A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.
Claims18
A data processing method for a system including a controller and a nonvolatile memory device having at least one array of nonvolatile memory cells arranged in a plurality of blocks, the method comprising:
- receiving an instruction including an address from a host;
- performing a first operation using a first address translation central processing units (CPU) in response to the instruction;
- and
- performing a second operation using a second address translation CPU in response to the instruction,
- wherein each of the first operation and the second operation is one of an address translation operation for the address, a wear leveling operation for the nonvolatile memory cells, and a bad-block management operation for the blocks.
A method of operating a controller in response to an instruction received from a host, the controller controlling a nonvolatile memory device accessed via a plurality of channels, the method comprising:
- selectively operating at least one of a first address translation central processing unit (CPU) and a second address translation CPU of the controller in response to the instruction, wherein the first and second address translation CPUs are respectively configured to translate a logical address received as part of the instruction into a corresponding physical address, generate wear level information for the nonvolatile memory cells of the nonvolatile memory device, and generate bad block information capable of managing bad blocks included in the nonvolatile memory device,
- wherein the first and second address translation CPUs are further respectively configured to change an address mapping table including the logical address and the corresponding physical address in response to at least one of the wear leveling information and the bad block information.
A data processing method comprising:
- receiving input data and instructions from a host in a controller;
- determining priorities of the instructions and distributing the instructions among a plurality of address translation central processing units (CPUs) according to the determined priorities;
- using a first address translation CPU among the plurality of address translation CPUs to translate a logical address received as part of an instruction distributed to the first address translation CPU to generate a corresponding physical address associated with the input data;
- using at least one of the plurality of address translation CPUs to generate wear leveling data for nonvolatile memory cells of the nonvolatile memory device and generate bad-block information capable of managing bad blocks of the nonvolatile memory device;
- distributing the input data and the corresponding physical addresses to a one of a plurality of flash memory controllers, wherein each one of the plurality of flash memory controllers is configured to control an access operation for flash memory chips of a non-volatile memory device using at least one of a plurality of channels extending between the controller and the non-volatile memory in response to at least one control signal provided by the plurality of address translation CPUs;
- and
- by operation of at least one of the plurality of address translation CPUs, loading an address mapping table, and then changing the loaded address mapping table on the basis of the wear leveling information and the bad-block information.
Dependencies are inferred from the claim text.