Scalable memory system

A memory device configured to:

• receive a first command including a device address corresponding to the memory device;
• execute at least one core operation in a first memory bank of the memory device in response to the first command;
• receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the memory device;
• and
• execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.

A memory system having serially connected memory devices, wherein at least one of the memory devices is configured to:

• receive a first command including a device address corresponding to the at least one memory device;
• execute at least one core operation in a first memory bank of the memory device in response to the first command;
• receive a second command during execution of the at least one core operation in the first memory bank, the second command including the device address corresponding to the at least one memory device;
• and
• execute, concurrently with the execution of one or more of the at least one core operation executed in the first memory bank, at least one core operation in a second memory bank of the selected memory device in response to the second command.