Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits

A computer, comprising:

• a central processing unit;
• an integrated peripheral bridge, interface controller, and Phase-Locked Loop (PLL) clock circuitry in a single chip, directly coupled to the central processing unit without any intervening PCI bus;
• a low voltage differential signal (LVDS) channel directly extending from the interface controller comprising at least two serial channels of unidirectional, differential signal pairs to convey data in opposite directions, wherein the LVDS channel conveys encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form;
• and
• wherein the PLL clock circuitry generates different clock frequencies, and the interface controller conveys the PCI bus transaction through the LVDS channel based on the different clock frequencies.

A printed circuit board, comprising:

• a central processing unit;
• a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus;
• a low voltage differential signal (LVDS) channel directly extending from the peripheral bridge comprising two unidirectional, serial channels of multiple differential signal line pairs to convey data in opposite directions, wherein the LVDS channel conveys address and data bits of a PCI bus transaction in serial form;
• and
• a network controller coupled to the central processing unit.

A computer, comprising:

• an integrated central processing unit and interface controller in a single chip;
• a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction;
• and
• a system memory directly coupled to the integrated central processing unit and interface controller.

A computer system, comprising:

• a computer with
• a connector configurable for coupling to a console;
• an integrated central processing unit, graphics subsystem and interface controller in a single chip;
• a first Low Voltage Differential Signal (LVDS) channel directly coupled to the interface controller, adapted to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the first LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction;
• wherein the integrated graphics subsystem directly outputs digital video display signals in a third differential signal channel;
• and
• wherein the integrated interface controller is configurable to convey the PCI bus transaction on different numbers of differential signal pairs.

A computer, comprising:

• an integrated central processing unit, graphics subsystem and interface controller in a single chip, wherein the integrated interface controller is directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels communicating encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;
• a connector adapted to convey digital video display signals from a differential signal channel directly connected to the integrated graphics subsystem, and a serial bit stream of encoded address and data bits of a PCI bus transaction in a second LVDS channel comprising unidirectional, differential signal pairs;
• and
• wherein the computer couples to a console through the connector.

A computer comprising

• an integrated central processing unit and graphics subsystem in a single chip directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels transmitting encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;
• an interface controller directly coupled to a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;
• a connector coupled to the interface controller adapted to convey a serial bit stream of encoded address and data bits of a PCI bus transaction from the second LVDS channel;
• and
• a console, wherein the computer is adapted to couple to the console through the connector.

A modular system, comprising:

• a computer comprising:
• a central processing unit directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of four or more, unidirectional, differential signal pairs transmitting data packets serially in opposite directions, wherein the data packets communicate encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form,
• a system memory directly connected to the central processing unit, and
• a connector adapted to convey digital video display signals and to transmit a serial bit stream of encoded address and data bits of a PCI bus transaction through a second LVDS channel comprising two sets of unidirectional, differential signal pairs in opposite direction;
• and
• a console, wherein the computer is adapted to couple to the console through the connector.

A computer, comprising:

• a central processing unit comprising an interface controller directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, multiple, differential signal pairs transmitting encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions, wherein the interface controller is configured to convey the PCI bus transaction through the LVDS channel in different numbers of differential signal pairs;
• a system memory directly connected to the central processing unit;
• a mass storage device coupled to the central processing unit;
• and
• a second Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, differential signal pairs transmitting data serially in opposite directions, wherein the second LVDS channel is a point-to-point data communication link.

A computer, comprising:

• an integrated central processing unit and graphics subsystem in a single chip;
• a first Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction, wherein the first LVDS channel conveys data using a Universal Serial Bus (USB) protocol;
• a system memory directly coupled to the integrated central processing unit and graphics subsystem;
• and
• a graphics memory directly coupled to the integrated central processing unit and graphics subsystem.

A computer, comprising:

• an integrated central processing unit and interface controller in a single chip;
• a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and interface controller to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form, wherein the LVDS channel comprises a first unidirectional, multiple, differential signal line pairs to convey data in a first direction and a second unidirectional, multiple, differential signal line pairs to convey data in a second, opposite direction;
• a socket for a system memory module, directly coupled to the integrated central processing unit and interface controller;
• and
• wherein the interface controller is configurable to convey the PCI bus transaction through the LVDS channel on different numbers of differential signal line pairs.