Method of operating data compression circuit and devices to perform the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMan Keun SEO, Dae Wook KIM, Hong Rak SON, Jun Jin KONG
Life of this patent
Estimating the term…
Abstract
A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.
Claims20
A method of operating a data compression circuit, the method comprising:
- receiving and storing a plurality of data blocks until a cache is full;
- and
- writing the data blocks, which have been stored in the cache, to a buffer memory when the cache is full.
A data compression circuit, comprising:
- a cache to receive and store a plurality of data blocks;
- a buffer memory to receive and store the data blocks output from the cache when the cache is full;
- and
- a compressed-data generation circuit to perform forced encoding on each of the data blocks regardless of repetitiveness of each data block.
9-10. (canceled)
A method of operating a data compression circuit, the method comprising:
- reading a plurality of reference data blocks neighboring each other from a buffer memory simultaneously based on an address;
- comparing one of the reference data blocks with a data block;
- and
- encoding the data block based on a result of the comparison.
A data processing system, comprising:
- a host to generate an input data stream including a plurality of data blocks;
- and
- a memory controller to transmit and receive the input data stream from the host, the memory controller comprising a data compression circuit that comprises:
- a cache to receive and store the plurality of data blocks,
- a buffer memory to store the plurality of data blocks within a plurality of internal memories when the cache is full such that the plurality of data blocks are each to be used as a plurality of reference data blocks to determine whether another data block to be processed is a repetition of one of the reference data blocks, and
- a compressed-data generation circuit to perform one of a plurality of types of encoding on the another data block based on the determination.
Dependencies are inferred from the claim text.