Reducing gate height variance during semiconductor device formation

A method for reducing gate height variance in a semiconductor device, comprising:

• removing a hard mask layer and a set of spacers from a first gate stack and a second gate stack, the first gate stack having a first dummy gate, and the second gate stack having a second dummy gate;
• depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate;
• removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate;
• and
• removing the set of dummy gates to reduce a height variance between the first gate stack and the second gate stack.

A method for reducing gate height variance in a semiconductor device, comprising:

• identifying a height variance between a first gate stack and a second gate stack of a semiconductor device, the first gate stack having a first dummy gate and the second gate stack having a second dummy gate;
• removing a hard mask layer and a set of spacers from the first gate stack and the second gate stack;
• depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate;
• removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate;
• and
• removing the set of dummy gates to reduce the height differential between the first gate stack and the second gate stack.