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US 2014/0192938 A1Published application
Signal processing circuit and signal processing method
AssigneeFujitsu Limited
InventorHirotaka TAMURA
Life of this patent
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Abstract
A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals.
Claims11
A signal processing circuit comprising:
- a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively;
- and
- a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal,
- wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals.
1 more element
A signal processing method comprising:
- delaying an analog signal via a delay line including delay elements and outputting analog signals with different delay times to a plurality of taps;
- sampling a signal from a first tap among the plurality of taps in a first phase that is in synchronization with a clock signal and outputting the first sampled signal;
- and
- sampling the signal from the first tap in a second phase that is in synchronization with the clock signal and outputting the second sampled signal.
1 more element
Dependencies are inferred from the claim text.