Memory cell operation
AssigneeMicron Technology, Inc.
InventorsRoy E. Meade, John K. Zahurak
Life of this patent
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Abstract
Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.
Claims21
1-19. (canceled)
A method for operating a memory cell, comprising:
- charging a capacitor coupled to the memory cell to a particular voltage level;
- and
- discharging the capacitor through the memory cell to program the memory cell, wherein the discharge of the capacitor provides a magnitude of current sufficient to program the memory cell from a first state to a second state and the capacitor is a stray capacitance that includes a conductive line parasitic capacitance.
A memory device, comprising:
- an array of memory cells;
- control circuitry coupled to the array to charge a capacitor coupled to a selected memory cell to a particular voltage level and provide a magnitude of current, by discharge of the capacitor, to the selected memory cell sufficient to program the selected memory cell from a first state to a second state;
- and
- a switch located between a voltage source and the selected memory cell, wherein opening the switch adjusts a bias applied to an access line corresponding to the selected memory cell.
A method of operating a memory cell, comprising:
- closing a switch that is coupled to the memory cell to apply a bias to an access line coupled to the memory cell to charge an access line parasitic capacitor;
- opening the switch to adjust the bias;
- discharging the access line parasitic capacitor through the memory cell, wherein the discharge provides a magnitude of current sufficient to program the memory cell from a first state to a second state;
- and
- charging a bit line parasitic capacitor via the discharge of the access line parasitic capacitor.
The method of claim 36, including providing a potential difference across the memory cell by adjusting a bit line bias.
Dependencies are inferred from the claim text.