Differential sense amplifier for solid-state memories

In an integrated circuit, a memory having at least one sense amplifier, the at least one sense amplifier comprising:

• a first pair of transistors having gate terminals connected to a first amplifier node and having, output terminals serially coupled between a power supply node, a second amplifier node, and a switch node;
• a second pair of transistors having gate terminals connected to the second amplifier node and having output terminals serially coupled between the power supply node, the first amplifier node, and the switch node;
• a first switch selectively coupling the first amplifier node to a first input of the sense amplifier;
• a second switch selectively coupling a first internal node to a second input of the sense amplifier;
• first capacitor coupled between the first internal node and the second amplifier node;
• a second capacitor coupled between the first amplifier node and a second internal node;
• a third switch selectively coupling a control node to the second internal node;
• a fourth switch selectively coupling the second internal node to a third input of the sense amplifier;
• a fifth switch selectively coupling the second amplifier node to a fourth input of the sense amplifier;
• a sixth switch selectively coupling the first internal node to the control node:
• a first precharge switch selectively coupling the first input of the sense amplifier to a power supply node:
• a second precharge switch selectively coupling the second input of the sense amplifier to ground;
• a third precharge switch selectively coupling, the third input of the sense amplifier to ground;
• and
• a fourth precharge switch selectively coupling the fourth input of the sense amplifier to the power supply node;
• wherein the first and second switches operate in response to a first control signal, the fourth and fifth switches operate in response to a second control signal, the first and second precharge switches operate in response to a control signal that is a logical complement to the first control signal, and the third and fourth precharge switches operate in response to a control signal that is in logical complement to the second control signal.

A method of reading data from a memory having at least one pair of bit lines, comprising the steps of:

• precharging a first one of the pair of bit lines to a first voltage;
• precharging a second one of the pair of bit lines to a second voltage different from the first voltage;
• DC-coupling the first one of the pair of bit lines to a first input of a cross-coupled amplifier;
• AC-coupling the second one of the pair of bit lines to a second input of the cross-coupled amplifier;
• enabling a memory cell coupled between the first and second one of the pair of bit lines;
• injecting a charge of current into the first input of the cross-coupled amplifier;
• and then
• enabling the cross-coupled amplifier.