Multi-port memory device with serial input/output interface
OwnerChang-Ho Doinventor
Life of this patent
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Abstract
A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.
Claims16
A multi-port memory device comprising:
- a plurality of serial input/output (I/O) data pads;
- a plurality of ports configured to perform the serial I/O data communication with external devices through the serial I/O data pads;
- a plurality of banks configured to perform a parallel I/O data communication with the ports;
- a plurality of first data buses configured to transfer first signals from the ports to the banks;
- a plurality of second data buses configured to transfer second signals from the banks to the ports;
- a plurality of switching units configured to couple the first data buses to the second data buses one to one in response to a mode enable signal, to transfer the first signals outputted from each of the ports to the same respective port of origin via the coupled first and second data buses, or to transfer the first signals outputted from the ports to the banks via the first data buses;
- and
- a plurality of output drivers configured to interrupt the transferring of the second signals from the banks to the second data buses in response to the mode enable signal.
A multi-port memory device comprising:
- a plurality of banks;
- a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices and a parallel I/O data communication with the banks;
- a switching unit configured to transfer from each of the plurality of ports signals originally intended for the banks but redirected to the same respective port as originally transferred from, the signals being redirected back to the same respective port during a test mode for testing the plurality of ports without regard to the plurality of banks;
- and
- a plurality of output drivers configured to intercept a transferring of the banks to the ports during a test mode.
Dependencies are inferred from the claim text.